Gate Arrays are Integrated Circuits whit the following primary elements:
(1) An array of core cells; and PA1 (2) An array of interconnects.
Core cells (also referred to as logic module cells) can implement a variety of logic functions. The selection of a core cell is a key design problem in the development of the gate array architecture. A core cell of a gate array device is characterized among others, by its number of inputs, area, levels of logic required per function, etc. Those characteristics of a logic cell directly affect the frequency and noture of interconnects used which in turn translates to overall performance and area of a given design mapped into a particular gate array.
In the field of gate arrays, designers over the years have spent a great deal of time and effort in designing and analyzing gate array cells. Careful attention has been paid to the size of cells, placement of cells, the number of cells and the like. This effort has been directed to creating a library of cells which are particularly useful in defining a gate array which will have a sufficient number of functions available so as to suit the needs of the circuit designer seeking to use the gate array. It is an additional objective of the gate array designer to be able to provide the functionality desired by logic designers while requiring as few gate array chips as possible.
In the past, designers have attempted to create gate arrays that have logic cells that achieve these objectives. The fact that so many gate arrays have been produced with various logic cells is a testament to this fact and to the fact that designers have not developed a logic cell for gate arrays that is deemed by designers to be clearly better than others. Analysis of logic cells for existing gate arrays demonstrates that they can perform a varying number of functions utilizing a single base logic cell. These cells can then be interconnected with other logic cells of the same or different design to produce other functions. The principal objective of the cell designer, therefore, is to produce the greatest possible functionality per unit area of the chip in a configuration which permits high utilization of the cells on the chip.
Other factors enter into the design of a gate array cell. For instance, cell inputs and outputs are expensive and, accordingly, designers attempt to minimize their number. On the other hand, increasing the number of inputs and outputs permits assembling a cell that operates on a greater number of input data bits thereby dramatically increasing the number of functions that can be performed by each cell. However, if the cell is used by circuit designers for only four input functions, for example, a cell with more inputs and functions may prove to be wasteful. Accordingly, logic cell design is an exercise in balancing conflicting factors.